The power consumption of an integrated circuit can be reduced by completely shutting down one or more modules (circuits) of the integrated circuit. These circuits are shut down during one or more low-power periods. These shut-down circuits are also known as power-gated circuits as they receive a gated supply during non-low-power periods and do not receive the gated supply during the low-power period.
State retention power gating (SRPG) involves shutting down (by an on-die switch or often by multiple switch devices) the power-gated circuits while saving their status during low-power periods. Integrated circuits in which this technique is implemented include retention circuits that are powered by the continuous (retention) power supply and store, during each low-power period, state information reflecting a state of a power-gated circuit.
The low-power period ends by performing a power up process (also referred to recovery process) during which the gated supply voltage is provided to the power gated circuit (by connection of the gated supply to main continuous supply by a switch device) and then state information is sent to the power gated circuits.
A typical integrated circuit includes a very large number (hundreds, thousands, and even more) of SRPG flip-flops, each including a state retention circuit and a power gated circuit.
Retention circuits are usually fed by a local continuous power grid that can be weak in the sense of the amount of power it can convey and is connected to the main continuous power grid and has a low local intrinsic capacitance and therefore is susceptible to noise. This noise can be caused by e.g. powering up multiple power gated circuit components during a power up process that ends the low-power period. This power up process comprises charging the intrinsic capacitance of the power gated circuit, accompanied by large main continuous power supply current drain, causing (this current-induced) power grid voltage sag and ground voltage bounce (also known as IR-drop). Obviously, the retention power grid connected to the main continuous power grid outside the power gated circuit, becomes noisy as well. The noise cannot be adequately suppressed by the retention power grid and can cause retained state information errors. In order to eliminate such noise, it is known to very slow increment the gated supply voltage level during the powering up process, in order to reduce the mentioned current drain and to e.g. connect the retention circuits to the power gated circuits by multiple switch devices in a sequential manner or to establish a significant power switch impedance during the powering up process. The attempt to eliminate completely the retention power grid noises usually has highest priority compare to the other power up process parameters. Hence, the powering up process is usually very long. The duration of this process often determines whether or not is worth to use the low power mode, and is therefore critical for the integrated circuit power consumption reduction.